The RRAM is a MIM (Metal/Insulator/Metal) capacitor structure, which allows the device to be converted reversibly between a HRS (High Resistance State) and a LRS (Low Resistance State) by applying an electrical signal, so as to achieve data storage function. Because of excellent characteristics of the RRAM in terms of cell area, 3D (Three-Dimensional) integration, low power consumption, high erasure speed and multi-value storage, the RRAM has drawn high attention both at home and abroad.
Array frameworks of the RRAM may be divided into a passive cross array and an active array. In the passive cross array, each memory cell is defined by an upper electrode and a lower electrode consisting of word lines and bit lines intersected with each other, and the smallest memory cell area 4F2, where F is a feature size, can be achieved in a planar structure. The passive cross array may be multi-layer stacked to achieve a 3D storage structure, since it does not depend on a front end process of a semiconductor process. An effective cell area of each memory cell is only 4F2/N, where N is a number of stacked layers. However, a low resistance state of the RRAM in the passive cross array framework shows an ohmic conduction characteristic, and is prone to generate a crosstalk effect when a resistance value of an adjacent intersection point is read. Taking a 2×2 cross array shown in FIG. 1 as an example, if three adjacent intersection points, (1,2), (2,2) and (2,1), are in the low resistance state, a resistance read from the point (1,1) is always low resistance, no matter whether an actual resistance at the point (1,1) is in a high resistance state or the low resistance state. When a storage array becomes larger or multi-layer arrays are stacked, electricity leakage phenomenon will be more severe. In order to solve a misreading phenomenon caused by the crosstalk problem, a typical solution is to serially connect a diode or a non-linear resistor having rectification characteristics to the resistive device.
There are mainly two 3D integration approaches of the RRAM. One is a cross array multi-layer stacked structure, i.e., being formed by repeatedly preparing a 2D cross array structure and stacking multiple layers of the 2D cross array structures: and the other is the vertical cross array structure, i.e., rotating the conventional horizontal cross array structure by 90° and repeatedly extending in a horizontal direction to form a vertical 3D array structure.
The multi-layer stacked structure requires that each of layers of cross array structure is prepared respectively, which significantly improves production cost while a storage density per unit area is increased. Taking an N-layer stacked cross array as an example, it is typically produced by (2N+1) times of photolithograph, the photolithograph step accounting for about 30% of a total semiconductor production cost. However, the vertical 3D array structure only requires N+1 times of photolithograph, whose process cost is greatly reduced as compared to the multi-layer stacked structure.
For the multi-layer stacked structures, integration of a gated tube and a resistive unit may be implemented more conveniently by a planar process; while for the vertical cross array structure, the integration of the gated tube is very difficult. That is because, in the vertical array, the upper electrode of each column of the resistive units is formed by a trench filling process, and due to lacking of a patterning process on a single device, it is very difficult to integrate one gated tube on each of the resistive units. Currently, worldwide reports about the vertical cross array 3D structure are almost entirely based on a single R structure, as shown in FIG. 2, which will be greatly restricted in terms of its integration scale and read and write operations in the absence of the gated tube.